The present invention relates to an anneal technique for reducing an amount of electronic trap in a gate oxide film of a transistor, which is applied to a semiconductor device using an insulating film, which is formed by a chemical reaction of gas as material, as a passivation film.
A passivation film, which is formed of SiO.sub.2, Si.sub.3 N.sub.4, or SiO.sub.x N.sub.y (x, y denote arbitrary positive numbers each showing an atomic ratio), is often used in LSI. As an interlayer insulating film of a lower layer of the passivation film, there is used an insulating film of silicon glass series such as PSG, BPSG, ASG, BSP, CSG, etc.
The insulating film used as a passivation film has low hygroscopicity and water permeability, and the insulating film used as an interlayer insulating film has a property of easily absorbing water. The interlayer insulating film contains water permeated mainly in manufacturing the interlayer insulating film.
Water molecules in the interlayer insulating film is dispersed in the interlayer insulating film by heat generated in depositing the passivation film. At this time, water molecules neither transmit through the passivation film nor disperse to the outer portion of the semiconductor device. Water molecules disperse into the gate oxide film of the transistor in the semiconductor device. The reason is that the passivation film has a property of permeating water with difficulty (low water permeability).
Water molecules permeated into the gate oxide film of the transistor cause electronic trap in the gate oxide film so as to deteriorate a hot carrier life of the transistor.
To solve the above problem, for example, there is an anneal method for the purpose of removing water of the interlayer insulating film before depositing the passivation film. For example, this method is a well-known technique as disclosed in Japanese Patent Application KOKAI Publication No. 61-219141.
However, in this method, the anneal process must be performed in a cleaning room since the annealing is performed before depositing the passivation film. As a result, the manufacturing cost is increased.
Japanese Patent Application KOKAI Publication No. 61-219141 also discloses removal of water of the interlayer insulating film in a DRAM (dynamic random access memory). To reduce a failure ratio of pose-failure of DRAM, anneal temperature and time may be set to 350.degree. C. and one hour before forming the passivation film (plasma nitrogen film) as described in the above publication.
However, even if the conditions disclosed in the above publication are directly applied to a nonvolatile semiconductor memory such as EEPROM, the electronic trap in the gate oxide film of the memory cell transistor cannot be reduced to an extent that sufficient reliability can be obtained.
In other words, in the nonvolatile semiconductor memory such as EEPROM, it is necessary to review annealing temperature and time in more detail.
Thus, conventionally, the passivation film is formed to prevent water and impurity materials from being permeated from the outer portion of the semiconductor device (LSI). Due to this, the passivation film is formed of material having low hygroscopicity and water permeability. Since the water permeability of the passivation film is low, water of the interlayer insulating material disperses into the gate oxide film of the memory cell transistor to cause electronic trap.